Manufacturers of semiconductor devices routinely test their products at the wafer and packaged-device levels. The testing is usually carried out by a sophisticated system commonly referred to as automatic test equipment. The equipment generally drives waveforms to and detects outputs from one or more devices-under-test (DUT). The detected outputs are then compared to expected values to determine whether the device functioned properly.
Many logic devices include I/O pins that require three distinct voltage levels. Consequently, in order to test the full capabilities of such a device, semiconductor manufacturers often require the test equipment to have the capability of driving tristate waveforms to simulate the voltage levels. This capability, when provided, resides in the driver architecture for each channel that corresponds to a particular pin of the DUT.
Conventional driver architectures employed in automatic test equipment are usually designed on application specific integrated circuits (ASICs) that form part of the pin electronics for coupling to the DUT pins. The ASICs typically utilize bipolar, MOS, or GaAs technologies due to the high device densities achievable.
One conventional driver architecture that employs bipolar technology, illustrated in FIG. 1, is employed in the J973 Magnum tester, manufactured by Teradyne Inc., of Agoura Hills, Calif. The conventional architecture comprises a Class A switch configuration that pulls a variable current out of a buffer amplifier 10 to change the voltage level at the output V.sub.OUT. The buffer amplifier includes internal circuitry for generating a "high" voltage level Vh and an output resistance represented by resistor R1 (typically 50 ohms). A parallel network of differential pair switches 12 and 16 are coupled to the output and include respective programmable current sources (sinks) 14 and 18 to selectively draw current out of the buffer amplifier. The switches include respective pairs of complementary transistors Q1, Q2, and Q3, Q4 that activate in response to complementary logic signals A*, A, and B*, B.
An operational characteristic of a Class A driver is the constant operation of the programmable current sources I1 and I2. Typically, the current sources are programmed to sink specific currents to effect a desired voltage drop across R1, and achieve the desired voltage at VOUT. For the architecture illustrated in FIG. 1, the relationship for programming I1 is often (Vh-Vl)/R1, and for I2 the relationship is (Vh-Vt)/R1. Operating with the following parameters: Vh=2V, Vt=1V, Vl=0V, R1=50 ohms, VCC=7 volts and VEE=-6 volts, the respective currents for I1 and I2 correspond to 40 milliamps and 20 milliamps, respectively.
In operation, the parallel network of switches 12 and 16 responds to the timed logic signals A, A* and B, B* to activate and deactivate the proper transistors to produce the desired tristate waveform at the output VOUT. FIG. 2 illustrates a timing diagram regarding the sequencing of the transistors Q1-Q4 to achieve the tristate waveform 20. To set the output to Vh (2 volts), transistors Q2 and Q4 are deactivated while Q1 and Q3 are activated by the complementary logic signals A* and B*. As a result, the current out of the buffer 10 is minimized with little voltage drop across R1, placing VOUT at Vh (2 volts). Activating Q4 with logic signal B, and deactivating Q3 with signal B*, causes the second switch 16 to draw 20 milliamps of current out of the buffer 10 corresponding to the programmed level of current source I2. As a result, the output voltage drops to Vt (1 volt). To achieve the third voltage level Vl at the output VOUT, Q4 is switched off while Q2 simultaneously switches on, causing I2 to draw 40 mA across R1, and dropping VOUT to 0 volts.
While the conventional parallel switch driver architecture works well for its intended purposes, those skilled in the art have observed inaccuracies during the output transition of VOUT from Vt to Vl. The reason for the inaccuracy lies in the difficulty in simultaneously deactivating Q4 while activating Q2. Should Q4 turn off before Q2 turns on, as shown in FIG. 2, a "preshoot" 22 occurs that creates a ringing disturbance in the signal channel, requiring time to allow the disturbance to return to a steady state. This undesirably affects the accuracy of the tristate waveform, and indirectly reduces the effective speed of the tester.
Another problem with the conventional parallel architecture described above involves the power consumed during operation. As noted above, Class A drivers continuously maintain operation of the current sources I1 and I2. In the example above, current is always drawn by the sources, whether from the VCC rail (typically 7 volts), or the buffer amplifier 10. Consequently, the continuous total current sums to 60 milliamps, with a corresponding power consumption of 60 mA*13V=780 milliwatts. In some circumstances, tester users set Vl to Vt. As a result, the respective programmed currents drawn by I1 and I2 out of the buffer are both relatively high (often about 40 milliamps each), and consuming power on the level of about 80 mA*13V=1040 mW. These levels of power consumption are undesirable in many applications.
What is needed and heretofore unavailable is a tristate driver architecture for automatic test equipment having the capability of minimizing any preshoot transients during state transitions. Moreover, the need exists for a driver architecture that consumes minimal power during operation. The serial switch driver architecture of the present invention satisfies these needs.